In the processing of cryptographic information, which includes both encryption and decryption, multiplication modulo a large prime number is a key step in the ultimately desired process of exponentiation modulo a large prime number. For purposes of this processing cryptographic keys are employed. The length of the key is the principal determiner of security. The longer the key (in bits), the greater is the security level. Because of the ever increasing capabilities of data processing hardware, the length of keys to meet desirable levels of security has steadily increased. The cryptography engine described in the referenced patent is capable of expansion to meet these needs. However, it is noted that in the field of cryptography, the keys that are employed are often of varying size. This is reflective of the fact that different users of cryptography will seek different levels of security. For example, one user might be satisfied with a key length of 1,024 bits while another might insist on using 4,096 bit keys. While a cryptographic engine that is capable of processing 4,096 bit keys could also process 1,024 bit keys, the processing power of the hardware that is applied to that problem is essentially wasted.
In U.S. Pat. No. 7,080,110 referenced above, there is disclosed a circuit for performing multiplication modulo N, where N is a large prime number. Such circuits are useful for carrying out exponentiation operations modulo N. As mentioned above, these mathematical operations lie at the heart of a significant number of methods for encrypting and decrypting data. The circuits disclosed therein provide a powerful and flexible method for constructing and using concatenated arrays of what are referred to as “processing elements.” The similarity in structure of these processing elements is also seen to be of value in structuring a process in which operations are pipelined, thus increasing overall throughput. Accordingly, it is seen that the referenced issued patent provides a useful cryptographic engine which is used in the present invention. However, the present application describes a method of using the processing elements in a more flexible fashion to avoid the situation in which full hardware utilization fails to be achieved when there is a mix of cryptographic tasks presented to the engine.